Recently, semiconductor device integration has rapidly increased toward higher and higher densities. As a result, various geometric structures of the semiconductor device have been subjected to drastic changes.
FIG. 1 illustrates an example prior art side gate type semiconductor device in which a semiconductor substrate 1 is divided by active cell isolation devices 2 (e.g., shallow trench isolation devices) into field regions FR and an active region AR. A transistor 10 for selective switching current flow is located in the active region AR of the semiconductor substrate 1.
The transistor 10 is provided with, for example, a source/drain diffusion layer 15, a main gate pattern 12, a side gate pattern 14, a first gate insulating film 11 for electrically isolating the main gate pattern 12 from the semiconductor substrate 1, and a second gate insulating film 13, for electrically insulating the side gate pattern 14 from the main gate pattern 12 and for electrically insulating the side gate pattern 14 from the semiconductor substrate 1.
In the illustrated prior art side gate type semiconductor device, the scale of the main gate pattern 12 is a very important factor for fixing a size of the completed semiconductor device. If the scale of the main gate pattern 12 is large, the size of the active region AR must also be large, which, in turn, must inevitably make the size of the semiconductor device large, too.
Taking this sensitive situation into account, in the prior art, a precise photo-etching process is performed using a photoresist film pattern to secure micronization of the main gate pattern 12. However, in the prior art photo-etching process, since the photoresist pattern is formed by exposing the photoresist to a UV beam having a non-constant (i.e., variable) wavelength, if no other measure is taken, the profile of the resulting photoresist film pattern necessarily has a large difference from the desired profile. If the process for forming the main gate pattern 12 proceeds in spite of this situation, the resulting main gate pattern 12 cannot achieve a precision as high as the initially set scale. Thus, a simple application of the traditional photo-etching process to micronizing the main gate pattern 12 has many shortcomings.
Furthermore, even if a technology is developed for micronizing the main gate pattern 12 in a manner that meets the recent requirements, there will likely be other difficulties in applying such technology in practice. For instance, if the scale of the main gate pattern 12 is reduced without taking any other measure, the quality of the resulting semiconductor device can become poor due, in large part, to depletion caused by a current flow passage under the main gate pattern 12. (This current flow passage becomes substantially shorter as the scale of the main gate pattern 12 is reduced).
In summary, the problems associated with minimizing the scale of the main gate pattern 12, (e.g., increasing the current flow passage, etc.) create many limitations to substantially improving the quality of semiconductor devices including such gate patterns.
Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.